IXP23xx

Intel XScale® processor— A general-purpose 32-bit RISC processor
Microengines (MEs)—(Up to) Four 32-bit programmable engines.

Specialized for network processing; these engines handle the main data plane processing per packet. Major features include:
   Eight threads per ME with no overhead for context switching.
   8K x 40-bit instruction control store per ME.
   MEv2 instruction sets.
   1K 32-bit local memory per ME.
   256 general purpose registers.
   512 transfer registers.
   128 next neighbor registers

Media and Switch Fabric Interface (MSF) Interface for network framers and/or Switch Fabric.
  Contains receive and transmit buffers.
  Configurable to either of the following:
  Utopia 1/2/3, POS-2, SPI-3
  Utopia/POS Interface:

The Network Processor Engines (NPEs) are dedicated-function processors containing hardware coprocessors.


The Microengines have access to all shared resources (SRAM, DRAM, MSF,etc) as well as private connections between adjacent Microengines (referred to as next neighbors).
The Microengine provides support for software controlled multi-threaded operation.

There are eight hardware Contexts available in the Micro engine to allow for efficient context swapping.

The context switching is non-preemptive which means that a thread only swaps out when it voluntarily yields to other threads. When a thread yields the hardware swaps in the next thread that is ready to execute in round robin fashion. The round robin order is thread 0,1 ,2 ,3 4, 5,6 and 7 followed by thread 0 again.

Threads running on the same ME can also share data structures stored in local memory or absolute registers ME threads can share data with each other and with code running on the Intel XScale core by storing them in SRAM, DRAM or scratchpad memory.

Microengines follow RISC architecture and RISC processors are typically designed to execute one instruction on each clock cycle. Total 6stage pipeline.

Atomic operation means that a memory location is read, modified and written without another atomic operation intervening. To synchronize access to shared data structures in memory, IXP 23XX NP supports atomic operations for SRAM and Scratchpad memory.

Two MEs communicate using a scratch ring. One thread produces a message and the other thread consumes message from the ring.

.begin
.reg foo // defines a local variable named foo
.reg global foo // defines a global variable named foo
foo… // reference to foo is to the local variable
.endfoo … // reference to foo is to global variable

ALU operation on one or two source operands and deposit the result into the destination register
alu[index, index,  +, 4]      ; increase local memory index offset