ARM, Embedded FAQ

Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both busses. A von Neumann architecture has only one bus which is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time.
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What is RISC?

A reduced instruction set computer is a computer which only uses simple commands that can be divided into several instructions which achieve low-level operation within a single CLK cycle, as its name proposes “Reduced Instruction Set”.

What is CISC?

A complex instruction set computer is a computer where single instructions can perform numerous low-level operations like a load from memory, an arithmetic operation, and a memory store or are accomplished by multi-step processes or addressing modes in single instructions, as its name proposes “Complex Instruction Set ”.

RISC	CISC
1. RISC stands for Reduced Instruction Set Computer.	1. CISC stands for Complex Instruction Set Computer.
2. RISC processors have simple instructions taking about one clock cycle. The average clock cycle per instruction (CPI) is 1.5	2. CSIC processor has complex instructions that take up multiple clocks for execution. The average clock cycle per instruction (CPI) is in the range of 2 and 15.
3. Performance is optimized with more focus on software	3. Performance is optimized with more focus on hardware.
4. RISC processors are highly pipelined	4. They are normally not pipelined or less pipelined
5. Execution time is very less	5. Execution time is very high
6. Decoding of instructions is simple.	6. Decoding of instructions is complex
7. It does not require external memory for calculations	7. It requires external memory for calculations
8. The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC.	8. Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 CPUs.
9. RISC architecture is used in high-end applications such as video processing, telecommunications and image processing.	9. CISC architecture is used in low-end applications such as security systems, home automation, etc.

 

ARM Cortex M4:(ARMv7)
Thumb instruction set combines high code density with 32-bit performance

fast code execution permits slower processor clock or increases sleep mode time.

deterministic, high-performance interrupt handling for time-critical applications.

• optional Memory Protection Unit (MPU) for safety-critical applications
• extensive implementation-defined debug and trace capabilities:

• Pipeline:

  3-stage + branch speculation

Interrupts

Non-maskable Interrupt (NMI+ 1 to 240 physical interrupts

Interrupt Priority Levels

8 to 256 priority levels

Floating-Point Unit

Optional single precision floating point unit IEEE 754 compliant